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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
September 2008
FDMF6704A - XSTM DrMOS
Benefits
Ultra compact size - 6 mm x 6 mm MLP, 44 % space saving compared to conventional MLP 8 mm x 8 mm DrMOS packages. Fully optimized system efficiency. Clean voltage waveforms with reduced ringing. High frequency operation.
tm
The Xtra Small High Performance, High Frequency DrMOS Module
General Description
The XSTM DrMOS family is Fairchild's next-generation fullyoptimized ultra-compact integrated MOSFET plus driver power stage solution for high current, high frequency synchronous buck DC-DC applications. The FDMF6704A DrMOS integrates a driver IC, two power MOSFETs and a bootstrap Schottky diode into a thermally enhanced compact 6 mm x 6 mm MLP package. With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance and RDS(ON). This greatly reduces the package parasitics and layout challenges associated with conventional discrete solutions. The driver IC incorporates advanced features such as SMOD. A 5 V gate drive and an improved PCB interface [Low Side MOSFET exposed pad] ensure higher performance. This product meets the Intel 6 mm x 6 mm DrMOS pinout.
Features
Ultra- compact thermally enhanced 6 mm x 6 mm MLP package 84 % smaller than conventional discrete solutions. Synchronous driver plus FET multichip module. High current handling of 35 A. Over 93 % peak efficiency. Logic level PWM input. Fairchild's PowerTrench(R) 5 technology MOSFETs for clean voltage waveforms and reduced ringing. Optimized for high switching frequencies of up to 1 MHz. Skip mode SMOD [low side gate turn off] input. Fairchild SyncFETTM [integrated Schottky diode] technology in the low side MOSFET. Integrated bootstrap Schottky diode. Adaptive gate drive timing for shoot-through protection. Driver output disable function [DISB# pin]. Undervoltage lockout (UVLO). Fairchild Green Packaging and RoHS compliant. Low profile SMD package.
Applications
Compact blade servers V-core, non V-core and VTT DC-DC converters. Desktop computers V-core, non V-core and VTT DC-DC converters. Workstations V-core, non V-core and VTT DC-DC converters. Gaming Motherboards V-core, non V-core and VTT DC-DC converters. Gaming consoles. High-current DC-DC Point of Load (POL) converters. Networking and telecom microprocessor voltage regulators. Small form factor voltage regulator modules.
Power Train Application Circuit
5V CVDRV VDRV VCIN DISB# PWM Input OFF ON DISB# PWM SMOD# CGND CVCIN 12 V CVIN VIN BOOT PHASE VSWH PGND COUT CBOOT OUTPUT
Figure 1. Power Train Application Circuit
Ordering Information
Part FDMF6704A
(c)2008 Fairchild Semiconductor Corporation
Current Rating @ 350 kHz [A] 35
Input Voltage Typical [V] 8-14 1
Frequency Max [kHz] 1000
Device Marking FDMF6704A
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FDMF6704A Rev. C
FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Functional Block Diagram
VCIN VDRV BOOT HDRV VIN
Q1
DISB# PWM
Overlap Control VSWH
SMOD#
VDRV
Q2
CGND LDRV
PGND
Figure 2. Functional Block Diagram
Pin Configuration
PWM DISB# NC CGND LDRV VSWH VSWH VSWH VSWH VSWH
40 (CGND) (VIN)
SMOD# VCIN VDRV BOOT CGND HDRV PHASE NC VIN VIN 1 10
11
(VSWH) 31 20
VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND
30
21
Figure 3. 6mm x 6mm, 40L MLP Bottom View
VSWH VSWH PGND PGND PGND PGND PGND PGND PGND PGND 2
FDMF6704A Rev. C
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Pin Description
Pin
1 2 3 4 5, 37 6 7 8, 38 9-14 15, 29-35 16-28 36 39 40
Name
SMOD# VCIN VDRV BOOT CGND HDRV PHASE NC VIN VSWH PGND LDRV DISB# PWM
Function
When SMOD# = HI, low side driver is inverse of PWM input. When SMOD# = Low, low side driver is disabled. IC bias supply. Minimum 1 F ceramic capacitor is recommended from this pin to CGND. Power for low side driver. Minimum 1 F ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor from this pin to PHASE. IC ground. Ground return for driver IC. For manufacturing test only. This pin must be floated. Must not be connected to any pin. Switch node pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin. No connect. Power input. Output stage supply voltage. Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. Power ground. Output stage ground. Source pin of low side MOSFET(s). For manufacturing test only. This pin must be floated. Must not be connected to any pin. Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low). PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
Absolute Maximum Rating
Parameter
VCIN, VDRV, DISB#, PWM, SMOD#, LDRV to CGND VIN to PGND, CGND BOOT, HDRV to VSWH BOOT, VSWH, HDRV to GND BOOT to VDRV IO(AV) IO(peak) RJPCB Junction to PCB Thermal Resistance -55 Operating and Storage Junction Temperature Range VIN = 12 V, VO = 1.3 V fSW = 350 kHz fSW = 1 MHz
Min
Max
6 27 6 27 22 35 32 80 3.75 150
Units
V V V V V A A A C/W C
Recommended Operating Range
Parameter
VCIN VIN Control Circuit Supply Voltage Output Stage Supply Voltage
Min
4.5 8
*
Typ
5 12
Max
5.5 14
Units
V V
* May be operated at lower input voltage. See figure 8.
FDMF6704A Rev. C
3
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Electrical Characteristics
VIN = 12 V, TA = 25 C unless otherwise noted.
Parameter
Operating Quiescent Current VCIN UVLO UVLO Threshold UVLO COMP Hysteresis PWM, DISB# and SMOD# Input High Level Input Voltage Low Level Input Voltage Input Bias Current Propagation Delay Time High Side Driver Rise Time Fall Time Deadband Time Propagation Delay Low Side Driver Rise Time Fall Time Deadband Time Propagation Delay 250 ns Time Out Circuit 250 ns Time Delay
Symbol
IQ
Conditions
PWM = GND PWM = VCIN
Min
Typ
Max
2 2
Units
mA
3.0
3.2 0.2
3.4
V V V
2 0.8 -2 PWM = GND, delay between SMOD# or DISB# from HI to LO to LDRV from HI to LO. 10 % to 90 % 90 % to 10 % tDTHH tPDHL LDRV going LO to HDRV going HI, 10 % to 10 % PMW going LO to HDRV going LO 10 % to 90 % 90 % to 10 % tDTLH tPDLL VSWH going LO to LDRV going HI, 10 % to 10 % PWM going HI to LDRV going LO Delay between HDRV from HI to LO and LDRV from LO to HI. 15 2
V A ns
25 20 25 10 25 20 20 10
ns ns ns ns ns ns ns ns
250
ns
FDMF6704A Rev. C
4
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Description of Operation
Circuit Description
The FDMF6704A is a driver plus FET module optimized for synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1 MHz.
will work in synchronous mode. When the SMOD# pin is pulled low, the LS FET is turned off. The SMOD function does not have internal current sensing. This SMOD# pin is connected to a PWM controller which enables or disables the SMOD automatically when the controller detects light load condition. Normally this pin is Active Low.
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 4 for the relevant timing waveforms. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tPDLL). Once the LDRV pin is discharged below 1 V, Q1 begins to turn ON after adaptive delay tDTHH. To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tPDHL). Once the VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive delay tDTLH. Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged low, a secondary adaptive delay is initiated, which results in Q2 being driven ON after 250 ns, regardless of VSWH state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power convertor is sinking current and VSWH voltage does not fall below the 1 V adaptive threshold. The 250 ns secondary delay is longer than tDTLH.
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground referenced low RDS(ON) N-channel MOSFET. The bias for LDRV is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the driver is disabled (DISB = 0 V), LDRV is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (CBOOT). During start-up, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
SMOD
The SMOD (Skip Mode) function allows for higher converter efficiency under light load conditions. During SMOD, the LS FET is disabled and it prevents discharging of output caps. When the SMOD# pin is pulled high, the sync buck converter
PWM Input tDTHH DrvL DrvLLOW HDRV to SW Timeout SW SW_Low tPDLL tPDHL 250 ns 1V 90 % 1V tDTLH
Figure 4. Adaptive Gate Drive Timing 5
FDMF6704A Rev. C
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Typical Characteristics
VIN = 12V, VCIN = 5V, TA = 25C unless otherwise noted.
35 30 25 ILOAD, A 20 15 10 5 0 0 25 50 75
o
12 10 8 PLOSS, W
VIN = 12 V VOUT = 1.3 V L = 440 nH
fSW = 1 MHz 6 4
VIN = 12 V VOUT = 1.3 V fSW = 1 MHz L = 440 nH 100 125 150
fSW = 350 kHz 2 0 0 5 10 15 ILOAD, A 20 25 30 35 PCB Temperature, C
Figure 5. Safe Operating Area
Figure 6. Module Power Loss vs. Output Current
1.40 1.30 PLOSS (NORMALIZED) 1.20 1.10 1.00 0.90
VIN = 12 V VOUT = 1.3 V IOUT = 30 A L = 440 nH
1.16 1.14 1.12 PLOSS (NORMALIZED) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 VOUT = 1.3 V IOUT = 30 A L = 440 nH fSW = 350 kHz 6 8 10 12 14 16
0.80 200
300
400
500
600 fSW, kHz
700
800
900
1000
Input Voltage, V
Figure 7. Power Loss vs. Switching Frequency
Figure 8. Power Loss vs. Input Voltage
1.10 1.07 1.04 1.01 0.98 0.95 0.92 0.89 4.5 VIN = 12 V VOUT = 1.3 V IOUT = 30 A L = 440 nH fSW = 350 kHz 4.8 5.1 5.4 5.7 6.0
1.40 1.30 PLOSS (NORMALIZED) 1.20 1.10 1.00 0.90 0.80 0.8 VIN = 12 V IOUT = 30 A L = 440 nH fSW = 350 kHz
PLOSS (NORMALIZED)
1.1
1.4
1.7
2.0
2.3
2.6
2.9
3.2
Driver Supply Voltage, V
Output Voltage, V
Figure 9. Power Loss vs. Driver Supply Voltage
Figure 10. Power Loss vs. Output Voltage
FDMF6704A Rev. C
6
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Typical Characteristics
VIN = 12V, VCIN = 5V, TA = 25C unless otherwise noted.
1.045 1.040 Driver Supply Current, mA 1.035 PLOSS (NORMALIZED) 1.030 1.025 1.020 1.015 1.010 1.005 1.000 VIN = 12 V VOUT = 1.3 V IOUT = 30 A fSW = 350 kHz 275 330 Output Inductance, nH 385 440 45 40 35 30 25 20 15 10 5 0 200 300 400 500 600 fSW, kHz 700 800 900 1000 VCIN = 5 V
0.995 220
Figure 11. Power Loss vs. Output Inductance
Figure 12. Driver Supply Current vs. Frequency
60 fSW = 1 MHz Driver Supply Current, mA Driver Supply Current, mA 55 50 45 40 35 30 4.5 4.8 5.0 5.3 5.5 5.8 6.0 Driver Supply Voltage, V
50 49 48 47 46 45 44 43 42 41
VCIN = 5 V fSW = 1 MHz
40 -50
-25
0
25
50
o
75
100
125
150
Temperature, C
Figure 13. Driver Supply Current vs. Drive Supply Voltage
Figure 14. Driver Supply Current vs. Temperature
2.2 2.0 1.8 VIH 1.6 1.4 VIL 1.2 1.0 4.5 4.8 5.0 5.3 5.5 5.8 6.0 Driver Supply Voltage, V
2.2 2.0 1.8
VCIN = 5 V
PWM Threshold Voltage, V
PWM Threshold Voltage, V
VIH 1.6 1.4 VIL 1.2 1.0 -50
-25
0
25
50
o
75
100
125
150
Temperature, C
Figure 15. PWM Threshold Voltage vs. Driver Supply Voltage
Figure 16. PWM Threshold Voltage vs. Temperature
FDMF6704A Rev. C
7
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Typical Characteristics
VIN = 12V, VCIN = 5V, TA = 25C unless otherwise noted.
2.2 SMOD# Threshold Voltage, V SMOD# Threshold Voltage, V 2.0 VIH 1.8 1.6 1.4 1.2 1.0 4.5 4.8 5.0 5.3 5.5 5.8 6.0 Driver Supply Voltage, V 2.2 2.0 1.8 1.6 1.4 1.2 1.0 -50 VIH
VCIN = 5 V
VIL
VIL
-25
0
25
50
o
75
100
125
150
Temperature, C
Figure 17. SMOD# Threshold Voltage vs. Driver Supply Voltage
Figure 18. SMOD# Threshold Voltage vs. Temperature
2.2 2.0 VIH 1.8 1.6 1.4 1.2 1.0 4.5 4.8 5.0 5.3 5.5 5.8 6.0 Driver Supply Voltage, V
2.2 VCIN = 5 V 2.0 VIH 1.8 1.6 1.4 1.2 1.0 -50
DISB# Threshold Voltage, V
DISB# Threshold Voltage, V
VIL
VIL
-25
0
25
50
o
75
100
125
150
Temperature, C
Figure 19. DISB# Threshold Voltage vs. Driver Supply Voltage
Figure 20. DISB# Threshold Voltage vs. Temperature
FDMF6704A Rev. C
8
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Application Information
Supply Capacitor Selection
For the supply input (VCIN) of the FDMF6704A, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1 F, X7R or X5R capacitor. Keep this capacitor close to the FDMF6704A VCIN and PGND pins.
VCIN Filter
The VDRV pin provides power to the gate drive of the high side and low side power FET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values would be 10 Ohms and 1 F.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 21. A bootstrap capacitance of 100nF, X7R or X5R capacitor is adequate.
Typical Application
VIN 12V V5V 5V
VDRV PWM DISB# SMOD# VIN CGND
VCIN BOOT PHASE VSWH PGND CBOOT
FDMF6704A
VCC
EN
SMOD# PWM1
VDRV PWM DISB# SMOD# VIN CGND
VCIN BOOT PHASE VSWH PGND VOUT CBOOT
PWM Controller
PWM2 PWM3
FDMF6704A
PWM4 CGND VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH PGND CBOOT
Signal GND
Power GND
FDMF6704A
VDRV PWM DISB# SMOD# VIN CGND
VCIN BOOT PHASE VSWH PGND CBOOT
FDMF6704A Figure 21. Typical Application 9
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FDMF6704A Rev. C
FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Module Power Loss and Efficiency Measurement and Calculation
Refer to Figure 22 for module power loss testing method. Power loss calculation are as follows: (a) PIN = (VIN x IIN) + (V5V x I5V) (W) (b) POUT = VO x IOUT (W) = PIN - POUT (W) (c) PLOSS (d) Efficiency = 100 x POUT/PIN (%)
also be wide enough for high current flow. Other signal routing path, such as PWM IN and BOOT signal, should be considered with care to avoid noise pickup from VSWH copper area. 3. Output inductor location should be as close as possible to the FDMF6704A for lower power loss due to copper trace. 4. The PowerTrench(R) 5 MOSFETs used in the output stage are very effective at minimizing ringing. In most cases, no snubber will be required. If a snubber is used, it should be placed near the FDMF6704A. The resistor and capacitor need to be of proper size for power dissipation. 5. Place ceramic bypass capacitor and boot capacitor as close to VCIN and BOOT pin of FDMF6704A in order to supply stable power. Routing width and length should also be considered. 6. Ringing at the Boot pin is most effectively controlled by close placement of the capacitor. Do not add an additional Boot to PGND capacitor. This may lead to excess current flow through the Boot diode. 7. Use multiple Vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance.
PCB Layout Guideline
Figure 23 shows a proper layout example of FDMF6704A and critical parts. All of high current flow path, such as VIN, VSWH, VOUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. Following is a guideline which the PCB designer should consider: 1. Input bypass capacitors should be close to VIN and PGND pin of FDMF6704A to help reduce input current ripple component induced by switching operation. 2. It is critical that the VSWH copper has minimum area for lower switching noise emission. VSWH copper trace should I5V CVDRV VDRV VCIN DISB# PWM Input SMOD# DISB# PWM SMOD# CGND
V5V
A
CVCIN CVIN VIN BOOT PHASE VSWH PGND V VO CBOOT
IIN
A
VIN
IOUT COUT
A
VOUT
Figure 22. Power Loss Measurement Block Diagram
Figure 23. Typical PCB Layout Example (Top View)
FDMF6704A Rev. C
10
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FDMF6704A High Frequency, High Efficiency, Ultra Compact DrMOS Module
Dimensional Outline and Pad layout
FDMF6704A Rev. C
11
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Rev. I36
(c) 2008 Fairchild Semiconductor Corporation
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